
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   01:35:45 02/02/2011
-- Design Name:   DMA
-- Module Name:   E:/test_dma/tb_dma.vhd
-- Project Name:  test_dma
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: DMA
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY tb_dma_vhd IS
END tb_dma_vhd;

ARCHITECTURE behavior OF tb_dma_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT DMA
	PORT(
		Reset : IN std_logic;
		Clk : IN std_logic;
		RCVD_Data : IN std_logic_vector(7 downto 0);
		RX_Full : IN std_logic;
		RX_Empty : IN std_logic;
		TX_RDY : IN std_logic;
		ACK_out : IN std_logic;
		DMA_ACK : IN std_logic;
		Send_comm : IN std_logic;    
		Databus : INOUT std_logic_vector(7 downto 0);      
		Data_Read : OUT std_logic;
		Valid_D : OUT std_logic;
		TX_Data : OUT std_logic_vector(7 downto 0);
		CS : OUT std_logic;
		Write_en : OUT std_logic;
		OE : OUT std_logic;
		Address : OUT std_logic_vector(7 downto 0);
		DMA_RQ : OUT std_logic;
		READY : OUT std_logic
		);
	END COMPONENT;

	--Inputs
	SIGNAL Reset :  std_logic := '0';
	SIGNAL Clk :  std_logic := '0';
	SIGNAL RX_Full :  std_logic := '0';
	SIGNAL RX_Empty :  std_logic := '0';
	SIGNAL TX_RDY :  std_logic := '0';
	SIGNAL ACK_out :  std_logic := '0';
	SIGNAL DMA_ACK :  std_logic := '0';
	SIGNAL Send_comm :  std_logic := '0';
	SIGNAL RCVD_Data :  std_logic_vector(7 downto 0) := (others=>'0');

	--BiDirs
	SIGNAL Databus :  std_logic_vector(7 downto 0);

	--Outputs
	SIGNAL Data_Read :  std_logic;
	SIGNAL Valid_D :  std_logic;
	SIGNAL TX_Data :  std_logic_vector(7 downto 0);
	SIGNAL CS :  std_logic;
	SIGNAL Write_en :  std_logic;
	SIGNAL OE :  std_logic;
	SIGNAL Address :  std_logic_vector(7 downto 0);
	SIGNAL DMA_RQ :  std_logic;
	SIGNAL READY :  std_logic;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: DMA PORT MAP(
		Reset => Reset,
		Clk => Clk,
		RCVD_Data => RCVD_Data,
		RX_Full => RX_Full,
		RX_Empty => RX_Empty,
		Data_Read => Data_Read,
		TX_RDY => TX_RDY,
		ACK_out => ACK_out,
		Valid_D => Valid_D,
		TX_Data => TX_Data,
		CS => CS,
		Write_en => Write_en,
		OE => OE,
		Address => Address,
		Databus => Databus,
		DMA_ACK => DMA_ACK,
		Send_comm => Send_comm,
		DMA_RQ => DMA_RQ,
		READY => READY
	);
		
	
	
	-- Clock generator
  p_clk : PROCESS
  BEGIN
     Clk <= '1', '0' after 25 ns;
     wait for 50 ns;
  END PROCESS;
  
  p_reset : PROCESS
  begin
		Databus<="10101010" ,"10101111" after 550 ns,"11011011" after 600 ns,"10101111" after 700 ns, "10101100" after 800 ns;
		--RCVD_Data <= "10101010" ,"10101111" after 550 ns,"11011011" after 600 ns;--rx by the dma
		Reset <= '0', '1' after 10 ns;
		--tst for rx
		RX_Empty <='0','1' after 650 ns, '0' after 20000 ns, '1' after 30000 ns;
		RX_Full<='0';
		DMA_ACK<='0','1' after 500 ns,'0' after 800 ns,'1' after 20500 ns;
	---tx-------------------------	
		
		ACK_out<='0','1' after 850 ns,'0' after 900 ns,'1' after 950 ns;
		TX_RDY<='0','1' after 750 ns;
		Send_comm<='0','1' after 700 ns, '0' after 19000 ns;
  wait for 100000 ns;
  
  end process;

END;
